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Intel manufacturing executive Chris Auth says backside power delivery gives Intel’s 14A process a way to use High-NA EUV lithography with less demanding front-side pitch requirements. CTO Pushkar Ranade says Intel is close to TSMC in technology, but still trails in manufacturing scale and must deliver strong yields and on-time production ramps.
Intel manufacturing executive Chris Auth said the company’s backside power delivery design lets it use High-NA EUV lithography on its process technology by easing some front-side pitch requirements, while CTO Pushkar Ranade said Intel is close to TSMC in technology but still must close a substantial gap in manufacturing scale. Their comments on the Dwarkesh podcast frame Intel’s 14A process as a customer offering and emphasize that timely execution and high yields matter more than a small difference in performance, power or area.
Auth, Intel’s vice president and general manager for manufacturing development and customer engagement, said moving power delivery circuitry to the wafer’s backside frees space on the front side, where transistors and signal connections are located. He said that design choice reduces some of the pitch demands on front-side features and makes it possible to print them directly with High-NA EUV. Pitch is the spacing between features in a circuit; tighter pitches require more demanding patterning.
Auth contrasted Intel’s approach with TSMC’s. He said TSMC has tighter front-side pitch requirements because it does not use backside power delivery in the same way, and that TSMC therefore relies on double-patterning EUV for those features. This is Auth’s explanation of the manufacturing trade-off; the discussion does not provide independent comparative cost or yield data to quantify the claimed advantage.
Auth said Intel’s 14A process is available as an option in its process design kit and that the company is discussing it with customers individually. The remarks indicate a customer-engagement stage, but do not identify customers, commitments, production volumes or a firm deployment schedule.
High-NA EUV Is Intel’s 14A Bet. Scale Is the Test.
Intel executives say backside power delivery gives 14A more room to use High-NA EUV. They say a small gap in chip metrics matters less than manufacturing on schedule, at high yields, and in volume.
“A few percent” behind can be manageable. A generation behind is different.Pushkar Ranade, Intel CTO • Dwarkesh podcast
Move power to the back. Make room on the front.
Chris Auth’s explanation: backside power delivery eases some front-side pitch demands, letting Intel print certain features directly with High-NA EUV.
Backside power
Power-routing circuitry moves to the wafer’s reverse side, freeing front-side space for transistors and signal connections.
High-NA EUV
Auth says the layout reduces some pitch requirements, making direct printing possible for the features he described.
Intel’s account of TSMC
Auth says TSMC has tighter front-side pitch requirements and relies on double-patterning EUV for those features.
Specifications matter. Factory execution decides.
Ranade framed Intel’s challenge as a combination of competitive technology and the ability to manufacture reliably at scale.
Build a dependable ramp
Ranade said Intel may be a few percent behind in performance, power, or area density. He argued that staying on schedule and reaching high yields matter more for a rapid, large-scale ramp.
Bars illustrate the emphasis in Ranade’s remarks; they are not measured performance data.
Technology proximity is not factory parity
Ranade described Intel as close to TSMC in technology while acknowledging that TSMC is a much larger wafer manufacturer and that catching up in scale will take time.
For customers, process specifications have limited value if capacity, yield, or delivery timing cannot support their product plans.
These are Intel executives’ assessments. The discussion did not provide independent benchmarks or comparative manufacturing data.
“14A is an option in the PDK today and we’re handling it as a customer by customer discussion.”
Chris Auth • IntelWhat the discussion establishes—and what it leaves open.
Intel described its technical rationale and priorities. It did not disclose independent comparative results or confirm commercial readiness.
A process option is not a production commitment
Intel said 14A is available as an option in its process design kit and is being discussed with customers individually. No customers, commitments, production volumes, or firm deployment schedule were named. The podcast also supplied no comparative cost, yield, performance, power, or area-density figures for Intel and TSMC.
Four things to keep in perspective.
What did Intel say about High-NA EUV?
Auth said backside power delivery eases some front-side pitch requirements, allowing Intel to use High-NA EUV directly for the features discussed. This is Intel’s account, not an independent cost or yield comparison.
Is 14A confirmed for mass production?
No. Intel said 14A is a PDK option in customer-by-customer discussions. No adoption, order, production date, or volume commitment was confirmed.
What did Ranade say about TSMC?
He described Intel as close in technology but behind in manufacturing scale. He said closing that scale gap will take time and emphasized execution, yields, and on-time ramps.
Is the “few percent” gap independently verified?
No detailed benchmark, product comparison, or measurement method was provided. The estimate is Ranade’s characterization, not an independently established comparison.
Execution Will Define Intel’s Challenge
Intel’s comments matter because the company is trying to compete with TSMC not just on transistor design, but as a supplier capable of manufacturing chips at scale. A lithography approach that suits Intel’s circuit layout could affect process complexity and cost, but a technical rationale alone does not show that the process will deliver competitive yields or meet customer timelines.
Ranade said Intel may be a few percent behind on performance, power or area density, but argued that such a gap matters less than a whole-generation difference. He placed greater weight on being on schedule and achieving high yields for rapid, large-scale production ramps. That distinction is central for customers deciding whether to design products for a process: a competitive specification has limited value if manufacturing capacity, yield or delivery timing falls short.
The remarks are Intel executives’ assessment of the company’s position, not an independent benchmark comparing Intel and TSMC. They also do not establish that Intel has closed the broader production-scale gap Ranade acknowledged.
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Backside Power and High-NA EUV
Backside power delivery moves power-routing circuitry from the front of the silicon wafer to its reverse side. That can leave more room on the front for transistors and the connections that carry signals. Auth’s argument is that this layout gives Intel more flexibility in front-side pitch, allowing use of High-NA EUV without the same patterning approach he says TSMC needs.
High-NA EUV is a lithography technology designed to print smaller features at higher resolution. The discussion describes a pitch range of roughly 16 to 8 nanometers and says a single exposure may avoid some multi-patterning steps. These are general process considerations; the podcast remarks do not supply a direct cost comparison or confirm specific production outcomes for Intel 14A.
Intel’s comments focus on 14A, after earlier reports had discussed High-NA EUV in connection with the 18A node. Separately, the podcast included Intel component-research executive Jack Kavalieros discussing technical hurdles for stacking n-type and p-type transistors: vertical connections between the stacked devices become harder to form and fill as structures shrink. That discussion illustrates the manufacturing challenges beyond lithography, but does not change the status of 14A customer discussions.
“14A is an option in the PDK today and we’re handling it as a customer by customer discussion.”
— Chris Auth
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14A’s Customer and Production Status
The discussion does not identify which customers are evaluating 14A, whether any have made commitments, or when the process could enter volume production. Intel’s statement that 14A is an option in its design kit does not by itself confirm customer adoption or manufacturing readiness.
There are also no comparative figures for Intel’s or TSMC’s process yields, costs, performance, power consumption or area density in the remarks. Ranade’s “few percent” characterization is his assessment, and the specific benchmarks and products behind it were not detailed. The discussion does not establish whether TSMC’s schedule is changing or how any timetable comparison would affect Intel’s plans.
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Customer Talks and 14A Milestones
The next evidence to watch for is whether Intel names 14A customers, provides a production timetable, or reports progress on yields and manufacturing readiness. Customer design decisions and subsequent production ramps would help show whether Auth’s proposed High-NA EUV approach can work at commercial scale.
Until Intel provides those details, its comments establish the company’s technical argument and competitive priorities, but not the outcome of the 14A program. Further statements from Intel or customers would clarify adoption, while comparable public manufacturing data would be needed to assess performance against TSMC.
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Key Questions
What did Intel say about High-NA EUV?
Chris Auth said backside power delivery eases some front-side pitch requirements, allowing Intel to use High-NA EUV directly for those features. This is Intel’s account of its process approach, not a published independent comparison of cost or yield.
Is Intel 14A confirmed for mass production?
No production date or volume commitment was provided. Auth said 14A is an option in Intel’s process design kit and is being discussed with customers individually; the company did not name customers or confirm orders.
What did Ranade say about Intel’s position against TSMC?
Ranade said TSMC is a much larger wafer manufacturer and that catching up in scale will take time. He described Intel as close in technology, while saying execution, high yields and on-time production ramps matter more than a few percentage points in performance, power or area.
Did Intel provide data proving it is only a few percent behind?
No detailed benchmark, product comparison or measurement method was given. The few-percent estimate is Ranade’s characterization, and the remarks do not independently verify it across Intel and TSMC processes.
Source: Wccftech
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