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Micron plans to use wafer bonding with its upcoming 1ε DRAM process, then adopt High-NA EUV lithography for later DRAM generations. It is also developing vertical high-bandwidth memory and vertical edge inference memory designed to sit directly on processors; timing and product specifications have not been disclosed.
Micron plans to introduce wafer bonding with its upcoming 1ε DRAM process and use High-NA EUV lithography for subsequent generations, according to Tom’s Hardware. The approach follows the company’s decision to drop 4F2 memory cells from its roadmap and is part of its effort to keep scaling DRAM as rivals pursue smaller transistor designs.
The reported plan sets out a change in how Micron intends to advance its DRAM technology. Rather than relying on the 4F2 memory-cell design it has removed from its roadmap, the company intends to use wafer bonding alongside its forthcoming 1ε process technology. Tom’s Hardware describes High-NA EUV as a technology Micron plans to adopt for later DRAM generations, not as a confirmed feature of the 1ε process.
The report also says Micron is developing two memory concepts intended for direct integration on top of processors: vertical high-bandwidth memory (vHBM) and vertical edge inference memory (vEIM). These are described as development efforts. No launch schedule, product specifications, manufacturing details or customer plans are provided for either design.
The stated competitive pressure is that rivals are planning to use smaller DRAM transistors toward the end of the decade. The information available does not specify which competing products or process generations are being compared, nor provide performance, density or cost figures for Micron’s planned technologies. The plans indicate a direction, but do not establish how much they will improve memory products.
Micron’s Alternative DRAM Scaling Route
DRAM makers need to increase memory density and capability while managing the demands of manufacturing newer generations. Micron’s reported decision to leave 4F2 cells off its roadmap makes its alternative methods relevant to the company’s competitive position: it is turning to wafer bonding for an upcoming process and plans to use High-NA EUV in later generations.
If developed and brought into production, these techniques could shape how Micron continues scaling memory as competitors pursue smaller transistors. But the report provides no benchmarks or manufacturing targets, so it is not possible to compare the expected outcome with rivals’ plans. The processor-stacked vHBM and vEIM concepts point to a separate potential change: placing memory closer to computing hardware. Their practical value will depend on details that have not yet been disclosed, including capacity, bandwidth, power use, cost and availability.
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From 4F2 Cells to New Processes
Micron’s roadmap change is the immediate backdrop to the reported plans. Tom’s Hardware says the company has jettisoned 4F2 memory cells from its roadmap, leaving it to pursue other methods to keep scaling DRAM in coming years. The report does not explain why Micron removed that design or give a detailed account of the alternatives it considered.
The sequence described distinguishes two stages: wafer bonding with 1ε, followed by High-NA EUV for subsequent generations. It also distinguishes those process plans from the company’s work on vertical memory that would be integrated directly above processors. No specific product announcements or production milestones for the latter are included.
Key Process and Product Details Await
The reported plans do not include a date for the introduction of 1ε DRAM or a timetable for High-NA EUV adoption. It is also unclear how Micron intends to implement wafer bonding, which layers or components it would join, and what measurable gains the company expects from the change.
For vHBM and vEIM, the report gives no technical specifications, commercial launch dates or confirmation that either design has reached a particular development stage. It also does not identify the rivals planning smaller DRAM transistors or provide a common basis for comparing their roadmaps with Micron’s. These gaps mean the plans should be read as a reported technology direction, not as evidence of shipping products or achieved performance.
Watch for Process Milestones
The next useful milestones would be Micron’s disclosures on the 1ε process, including timing, technical details and how wafer bonding will be used. Further information will also be needed to establish when the company expects to apply High-NA EUV to later DRAM generations.
Details on the vertical memory projects could clarify whether vHBM and vEIM are intended for particular processor platforms and when they might become products. Until Micron provides schedules, specifications or performance data, the commercial implications of these developments remain open.
Source: Tom’s Hardware
Key Questions
What is Micron planning for its upcoming 1ε DRAM process?
According to Tom’s Hardware, Micron intends to introduce wafer bonding with its upcoming 1ε DRAM process. The report does not give a release date or explain the implementation in detail.
When will Micron use High-NA EUV?
The reported plan is to adopt High-NA EUV lithography for DRAM generations after 1ε. No specific generation or timing is provided.
What are vHBM and vEIM?
They are memory types Micron is developing: vertical high-bandwidth memory and vertical edge inference memory. The report says they are intended to be integrated directly on top of processors, but gives no specifications or launch plans.
Why is Micron changing its DRAM approach?
Micron has removed 4F2 memory cells from its roadmap and needs other ways to continue scaling DRAM, according to the report. Rivals are planning smaller DRAM transistors toward the end of the decade, though the report does not identify them or provide comparative performance data.
Source: Tom’s Hardware
